`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/24/2019 10:39:40 AM
// Design Name: 
// Module Name: counter_60
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module counter_60_24(
    input wire clk_in,
    input wire CLR, //posedge to clear
    output wire[3:0] tns,
    output wire[3:0] uts,
    output wire CO
    );
    
    parameter 
        max_num = 60;
    
    reg[5:0] num, next_num;
    
    
    always @ (posedge clk_in or posedge CLR) //D triggers module
    begin
        if (!CLR)
            num <= next_num;
        else num <= 0;
    end
    
    always @ (num) //output module
    begin
        if (num != max_num - 1)
            next_num = num + 1;
        else next_num = 0;
    end
    
    assign tns = num / 10;
    assign uts = num % 10;
    assign CO = (num == 0);
    
endmodule
